The present invention relates to a semiconductor integrated circuit, such as a DRAM and a pseudo SRAM, which comprises a refresh timer which generates a refresh signal for performing refreshing, and to a method of adjusting a cycle of the refresh timer. More particularly, the present invention relates to measures to reduce a consumption current which is associated with refreshing.
In recent years, spread of portable information telecommunication equipment has made it increasingly necessary to reduce a consumption current of a memory such as a DRAM. A DRAM, in particular, creates a consumption current associated with refreshing even during holding of data, and therefore, a reduction in a consumption current during holding of data is becoming an important task.
As shown in FIG. 14, a data holding time exhibits a temperature-dependency in a memory cell of a DRAM. As the temperature increases, a data holding time becomes shorter. To be specific, when a power source potential V.sub.CC is 3.6 V, each temperature increase of 10 degrees centigrade shortens a data holding time approximately by 1/1.5. A data holding time at the temperature of 75 degrees centigrade is only 1/10 of that at the temperature of 25 degrees centigrade. Considering this, in a DRAM which has a self-refreshing mode, to guarantee holding of data at a high temperature, a refreshing cycle is set extremely short to deal with a data holding time at a high temperature. Since this requires such a DRAM to perform refreshing more frequently than needed when the DRAM is used at a normal or a low temperature, the DR accordingly consumes a current more than needed.
Now, a description will be given on a technique which is disclosed in ISSCC Digest of Technical Papers, pp. 268-269, Feb. 1991 to reduce a refresh current at a low temperature by constructing a refresh timer which outputs a refresh signal to have a temperature-dependency so that a refreshing cycle becomes longer at a low temperature than at a high temperature.
A cause of a limit on a data holding time is a leak current which is generated at a PN junction in a memory cell transistor, both in a case shown in FIG. 15A where the transistor is an NMOS transistor and in a case shown in FIG. 15B where the transistor is a PMOS transistor.
Since the temperature-dependency of a data holding time is attributed to the temperature-dependency of a leak current at a PN junction, a temperature characteristic of a refresh timer may be matched to a temperature characteristic of a memory cell leak. Hence, in general, to ensure that refreshing intervals exhibit a temperature characteristic which is similar to that of a memory cell leak, the refreshing intervals of the refresh timer are controlled utilizing a leak speed of a memory cell.
In the following, one example of a circuitry diagram of a refresh timer which utilizes a leak speed of a conventional memory cell will be described with reference to FIG. 16.
As shown in FIG. 16, since the capacitance of one memory cell capacitor 203 is very small, to avoid an influence by an input capacitance of a potential comparing circuit 206, a noise, etc., about 1,000 memory cells are connected parallel to each other to form a memory cell block 201 which serves as a dummy of a main memory. That is, storage nodes 204 are linked to each other by wires and so are cell plate nodes 205, which connects all capacitors 203 parallel to each other. A change in a potential at any storage node 204 is supplied to the potential comparing circuit 206 and compared therein with a reference potential V.sub.REF. In general, the layout of the memory cell block 201 is designed as a refresh circuit, separately from that of the main memory.
Now, a circuitry operation of the refresh timer having such a structure as above will be described.
First, while the storage node 204 is charge up to a power source potential V.sub.CC through memory cell transistors 202 as shown in FIG. 16, in a timer circuit 208, an oscillation circuit 209 outputs an oscillation signal which serves as a refresh signal to an output terminal OUT, so that the main memory is refreshed in response to the oscillation signal. A counter circuit 210 counts the number of oscillations of the oscillation signal. When the number of oscillations reaches a count which is necessary to refresh all cells of the main memory, the counter circuit 210 outputs a signal to reset a latch circuit 207, thereby suspending oscillation of the oscillation circuit 209 (suspend of refreshing).
Next, when the latch circuit 207 is reset, the memory cell transistors 202 are turned off to separate the storage nodes 204 from a power source. As a result, charges held at the storage nodes 204 gradually decrease because of a leak at PN junctions at the memory cell transistors 202, so that potentials at the storage nodes 204 decrease.
Following this, the potential comparing circuit 206 sets the latch circuit 207 when the potentials at the storage nodes 204 drop down to the reference potential V.sub.REF. When the latch circuit 207 outputs a signal, the timer circuit 208 is reset to allow the oscillation circuit 209 to oscillate again, whereby the counter circuit 210 starts counting the number of oscillations again (start of refreshing). Meanwhile, when the latch circuit 207 outputs a signal, the memory cell transistors 202 are turned on to charge up the storage nodes 204 to the power source potential V.sub.CC once again. In this manner, a refreshing period and a refreshing suspend period are repeated alternately.
As described earlier, the refreshing suspend period is defined by a time which is necessary for a potential at the storage node 04 to drop from the power source potential V.sub.CC to the reference potential V.sub.REF. The storage nodes 204 are designed to exhibit a potential decrease speed which is approximately the same as the potential decrease speed of the main memory and a temperature characteristic which is approximately the same as that of the main memory during a drop. Hence, in this circuit, it is possible to set an optimal refreshing suspend period, i.e., optimal refreshing intervals, regardless of a temperature change.
By the way, since not all memory cells have the same data holding time, in the memory cell as a whole, a period during which refreshing is necessary must be defined by a memory cell which has the shortest data holding time. However, between the memory cell which has the shortest data holding time and a memory cell which has an average data holding time is different by about 30 times. FIG. 17 shows a result of measurement of a data holding time of a DRAM memory cell, with the power source potential V.sub.CC of 3.6 V and an ambient temperature of 75 degrees centigrade. As can be understood from FIG. 17, while memory cells having a short data holding time form a group, these cells account for only about 0.1% of all memory cells. Further, where a number of memory cells are connected parallel to each other so that the decrease speeds of potentials at the storage nodes are averaged as in the refresh timer described with reference to FIG. 16, even when the memory cell which has the shortest data holding time needs be refreshed, potentials at the storage nodes 204 do not decrease almost at all since the potentials at the storage nodes 204 are averaged in the refresh timer. For example, when the power source potential V.sub.CC is 5 V, the potentials at the storage nodes 204 are about 4.95 V, showing an extremely moderate decrease. Hence, the timing of the start of a refreshing period must be very susceptible even to a subtle change in the reference potential V.sub.REF, which makes it difficult to set optimal refreshing intervals.
A countermeasure to deal with this is to quickly decrease potentials at the storage nodes to the reference potential V.sub.REF. Proposals heretofore made include to ensure quick disappearance of charges in the storage nodes by setting the capacitance of the memory cell capacitor about 1/10 of the capacitance of the main memory as described in Laid Open unexamined Japanese Patent Application No. 4-259983, and to form a highly doped region in a substrate portion of the dummy memory cell to reduce an electric resistance value at the PN Junction of the transistor and to eventually increase a leak current by 1- or 1.5-order, as disclosed in Laid Open unexamined Japanese Patent Application No. 5-225777.
However, a semiconductor integrated circuit apparatus which comprises such a conventional refresh timer circuit has the following problems. That is, where the capacitance of the memory cell plates is set as 1/10, it is difficult to use the memory cells of the main memory as they are as memory cells of the semiconductor integrated circuit apparatus, and it is necessary to manufacture memory cells separately from the memory cells of the main memory. Such a structure cannot be regarded as a real dummy any more since there is a difference in the temperature characteristic, and therefore, it is difficult to properly set the refreshing intervals.
On the other hand, to decrease an electric resistance value, manufacturing of the memory cells definitely needs a few more steps, which is undesirable in terms of a cost. Moreover, the quantities of leak currents tend to be different from each other, which is another inconvenience.